Three-dimensional integration of semiconductor chips typically employs through-substrate vias (TSV's) that connect the front side of a semiconductor chip to a back side of the same semiconductor chip. Multiple semiconductor chips may be vertically stacked employing the through-substrate vias (TSV's). Such three-dimensional integration of semiconductor chips provides a higher device density per area than a single semiconductor chip without any vertical stacking, and reduces the size of a packaging substrate correspondingly.
While such benefits of three-dimensional integration of semiconductor chips are generally known, vertical stacking of multiple semiconductor chips requires die-to-die, die-to-wafer, or wafer-to-wafer alignment. Depending on the precision of the tool employed for such alignment, the overlay tolerance of the vertical stacking process may be from 0.5 microns to 5 microns, which must be considered into design to insure electrical functionality of stacked semiconductor chips. Specifically, the lateral dimensions of the through-substrate vias must be greater than the overlay tolerance of the tool employed for lateral alignment of multiple semiconductor chips. The feature size of the through-substrate vias is limited to dimensions greater than the overlay tolerance. While it is possible to reduce the overlay tolerance by employing accurate alignment tools, such tools are typically costly.
Further, the device density per single semiconductor chip is the same for stacked semiconductor chips and for non-stacked semiconductor chips. Thus, a minimum substrate area is required per each semiconductor device. In other words, while the areal device density in a vertical stack of semiconductor chips may be greater than the areal density of a non-stacked single semiconductor chip, the device density per substrate is the same. Thus, the cost of an initial (unprocessed) substrate per semiconductor device is the same between three-dimensionally stacked semiconductor chips and a non-stacked semiconductor chip.
In view of the above, there is a continuing need for a semiconductor structure that provides a high areal density at a low manufacturing cost.